The present disclosure relates to methods and systems for semiconductor manufacturing, and particularly to methods and systems for enhancing circuit performance, yield, and/or performance reliability of a semiconductor chip by employing multiplicate-layer-handling circuit simulation.
With continual scaling of dimensions in semiconductor devices and increase in the number of gates per chip, increasing yield and performance and circuit reliability of semiconductor chips has become a challenge for advanced semiconductor devices. Circuit simulation and reliability simulation of a chip design layout prior to manufacturing is extensively employed to maximize yield and performance of advanced semiconductor chips. As known in the art, the same type of device is employed throughout a semiconductor chip without any modification based on any particular concern.
Regarding circuit performance, a block in a semiconductor chip is designed according to a general design guideline without particular emphasis on performance or timing. During circuit simulations, a compromise is made to find operating conditions at which both power consumption and signal delay are maintained at acceptable levels. The frequency of chip operation can be reduced in order to bring about closure on power consumption and signal delay at all corners of operating conditions. The resulting design is a compromise between power consumption requirements and timing requirements.
Regarding circuit reliability, identical transistors are used to perform identical functions throughout a semiconductor chip. However, the environment in which these transistors are placed differs from transistor to transistor. The circuit reliability of each transistor is affected by different circuit reliability issues, which include, but are not limited to, thermal stress, operating temperature, electromigration, and pattern sensitivities. Such circuit reliability issues can be on a length scale of more than one chip block within a semiconductor chip. Thus, not all circuit reliability issues can be predicted before all blocks are placed in a design for a semiconductor chip. Variability in circuit reliability across a semiconductor chip has been taken as granted, and semiconductor chips have been designed with the expectation that some of the semiconductor devices would statistically fail. However, such an approach ultimately results in circuit reliability levels that are subject to random statistical variation depending on the types of environments that the semiconductor devices are subjected to due to arbitrariness in the design of the semiconductor chip.